The I2C protocol was engineered to replace the complexities of separate data bus and address bus lines with a straightforward 2-wire bus connection that would handle the communication between integrated circuits or devices inside microcontroller projects.
Information is sent out serially using one line for data (SDA) and one for clock (SCL). The 2 wires are in an open collector / drain configuration and pulled high using a resistor, which forms a wired AND circuit. A 7 bit addressing scheme is used, which provides the capacity to address 112 devices (sixteen addresses are reserved). The speed of the clock line is generally restricted by the bus capacitance, which is 400 pf. The transmission rate is generally four hundred kHz, although there are some implementations that run up to 2Mbps.
Even though most systems are arranged such that one device is the host or "master", and the other ones are set up as peripherals, or "slaves", any device on the bus line can become a master and take over the bus lines for data transference. If one device needs information transferred to or from another module it must wait till it sees no activity on the bus (SDA and SDL are high). It'll then issue a start signal, which causes all the other devices to enter a "listen" mode. The new master will then broadcast the 7 bit binary address of the proposed receiver along with a read / write bit, which indicates whether the transfer will be a read or write operation.
Bytes are always broadcast MSB first. The receiver with the matching address will reply with a confirmation pulse. The information byte (or bytes) are then transmitted according to the read/write status. After each data byte is sent, an acknowledgement pulse is sent from the receiving end to the transmitting end. When the transfer has been completed, the "master" issues a stop signal. This pulls the SCL line high followed by the SDA line, which frees the bus for another transfer.
The master always has complete control of the clock (SCL line) in a data transfer, if it is receiving or transmitting data. The "slave" can slow down the clock by holding it low temporarily if it's a slow module. The master can end the data transfer at any time by providing a stop signal, even in the middle of a byte transfer.
Information is sent out serially using one line for data (SDA) and one for clock (SCL). The 2 wires are in an open collector / drain configuration and pulled high using a resistor, which forms a wired AND circuit. A 7 bit addressing scheme is used, which provides the capacity to address 112 devices (sixteen addresses are reserved). The speed of the clock line is generally restricted by the bus capacitance, which is 400 pf. The transmission rate is generally four hundred kHz, although there are some implementations that run up to 2Mbps.
Even though most systems are arranged such that one device is the host or "master", and the other ones are set up as peripherals, or "slaves", any device on the bus line can become a master and take over the bus lines for data transference. If one device needs information transferred to or from another module it must wait till it sees no activity on the bus (SDA and SDL are high). It'll then issue a start signal, which causes all the other devices to enter a "listen" mode. The new master will then broadcast the 7 bit binary address of the proposed receiver along with a read / write bit, which indicates whether the transfer will be a read or write operation.
Bytes are always broadcast MSB first. The receiver with the matching address will reply with a confirmation pulse. The information byte (or bytes) are then transmitted according to the read/write status. After each data byte is sent, an acknowledgement pulse is sent from the receiving end to the transmitting end. When the transfer has been completed, the "master" issues a stop signal. This pulls the SCL line high followed by the SDA line, which frees the bus for another transfer.
The master always has complete control of the clock (SCL line) in a data transfer, if it is receiving or transmitting data. The "slave" can slow down the clock by holding it low temporarily if it's a slow module. The master can end the data transfer at any time by providing a stop signal, even in the middle of a byte transfer.
About the Author:
Embedded Adventures is an internet site that explores embedded electronics, including devices that can communicate using I2C such as a real time clock module or an air pressure sensor.
Posts
No comments:
Post a Comment